1. Field of the Invention
The present invention relates to generally to high speed data transmission on serial buses, and more specifically to a multiport physical layer interface for an IEEE 1394 serial bus node.
2. Description of the Related Art
A high speed serial bus for transfer of both asynchronous and isochronous data between a computer and peripheral devices (or nodes) is standardized by the IEEE in 1995 as xe2x80x9cIEEE Standard for High Performance Serial Busxe2x80x9d. An arbitration controller is provided between the link layer and multiple port transceivers to perform bus configuration, arbitration and packet transmission according to operating parameters stored in a register map. These operating parameters are loaded into the register map under control of the link layer processor. Each port transceiver is connected to two pairs of twister wire to transfer data at one of maximum speeds of 100 Mbps, 200 Mbps and 400 Mbps. The lowest of the maximum speed values of the multiple port transceivers is set into the register map as the top speed of a node. Before packet transmission, the set speeds of adjacent nodes are compared with each other and packet transmission begins with the lower of the two so that they operate at a common speed. As a means for extending the current inter-nodal maximum length of 4.5 meters, the use of plastic optical fibers has been proposed as described in xe2x80x9cDraft of Long Distance 1394 (100 m) Physical Layer As a Response to a DAVIC""s CFP8 Section 4.1.3.3 The A20 Reference Point, Home Networkxe2x80x9d, 17th DAVIC (Digital Audio-Visual Council) meeting in San Jose Jun. 16-20, 1997, CFP8xe2x80x94011 (8th Call for Proposals). Since the maximum speed of plastic optical fiber is 100 Mbps and since the IEEE 1394 requires that a maximum speed of 200 Mbps be stored in the register map as a default value, the use of a plastic optical fiber in combination with twisted pairs would result in a port transceiver receiving a 200 Mbps signal and repeating it on a port transceiver operating at the maximum speed of 100 Mbps. Therefore, there exists a need for manually setting the top speed of a node in a register map from a command source located at each access, rather than from a process on the upper layer.
It is therefore an object of the present invention to provide a physical layer interface having a speed setting circuit for setting the top speed of an IEEE serial bus node.
According to a first aspect of the present invention, there is provided a physical layer interface of an IEEE-1394 serial bus node comprising a plurality of port transceivers connected to respective serial buses, a controller connected to a link layer and the port transceivers, an encoder/decoder responsive to a control signal from the controller for performing data conversion between the link layer and the port transceivers, a repeater responsive to a control signal from the controller for repeating bus traffic between the port transceivers, a register for storing operating parameters of the controller, and a speed setting circuit for storing a lowest value of transmission speeds of the port transceivers in the register as a top speed of the node. The controller is arranged to read the stored speed value from the register, receive a speed value from another node and transmit packets at a lower one of the stored and received speed values.
According to a second aspect, the present invention provides a physical layer interface of an IEEE-1394 serial bus node comprising a plurality of port transceivers connected to respective serial buses, a controller connected to a link layer and the port transceivers, an encoder/decoder responsive to a control signal from the controller for performing data conversion between the link layer and the port transceivers, a repeater responsive to a control signal from the controller for repeating bus traffic between the port transceivers, a register for storing operating parameters of the controller, a first speed setting circuit located in a first port transceiver of the plurality of port transceivers for setting an operating speed of the first port transceiver, a second speed setting circuit located in a second port transceiver of the plurality of port transceivers for setting an operating speed of the second port transceiver, and a compare-and-select circuit for comparing the operating speed set by the first speed setting circuit with the operating speed set by the second speed setting circuit and storing a lower value of the set operating speeds in the register as a top speed of the node. The controller is arranged to read the stored speed value from the register, receive a speed value from another node and begin packet transmission at a lower one of the stored and received speed values.
Preferably, an optical port transceiver is implemented with a first driver having a pair of differential output terminals, the first driver receiving a control signal from the controller to develop a line state voltage across the output terminals, a light modulator for modulating a light beam according to the line state voltage to produce a first modulated light beam, a directional coupler for causing the first modulated light beam to propagate through an optical link in a first direction and detecting a second modulated light beam propagating through the optical link in a second direction opposite to the first direction, an optical detector for detecting a line state voltage from the second modulated light beam and producing therefrom a control signal, and a second driver having a pair of differential output terminals, the second driver receiving the control signal from the optical detector to develop a reconstructed line state voltage across the differential output terminals, the differential output terminals of the first and second drivers being connected together to the controller.